Via hole structures are common and are used to vertically connect metal or metalized layers in semiconductor devices. Via line structures are also used to connect metal layers. In some instances, via line structures are used inside the active area of a chip; in other instances, they are used outside of the active area.
FIG. 1 shows via hole structures 101-107 used with via line structures 108-109 on the same chip. FIGS. 2A and 2B show a conventional process for creating both via hole and via line structures on the same chip. Referring to FIG. 2A, a substrate 201 includes metal lines (or metalized lines) 202 and 203 for contact using a via line and via hole, respectively. It is appreciated that substrate 201 is used for illustrative purposes only and the structure of 201 may occur on top of other layers, not necessarily as part of a substrate, per se. Accordingly, lines 202 and 203 are described as being a first structure 201.
A barrier layer 204 is commonly deposited on top of structure 201. The barrier layer 204 is used to prevent oxidation or corrosion or migration of the material in metal lines 202-203. Metal lines 202-203 may include copper, aluminum, titanium, tantalum and tungsten, and other metals as known in the art. The barrier layer 204 may include SiCN, although other etch stopping compounds can be used. A thick SiCN layer is sometimes helpful as it seals a metal or metalized surface from moisture, corrosion, and metal migration without significantly increasing an interconnect capacitance between a covered metal or metalized layer and the conductive material filling the via hole or via line, so as to make the interconnect unusable.
On top of barrier layer 204 is another layer, for instance, a SiOCH layer 205 (also referred to as a SiOCH layer). Topping layer 205 is an oxide layer (for instance, silicon oxide, SiOx) 206. On top of the oxide layer 206 is a patterned resist layer 207, having patterned aperture 208 for a via line and 209 for a via hole.
FIG. 2B shows the structure of FIG. 2A after etching. Here, an anisotropic etch (for instance, reactive ion etching) may be used to create openings for the via line 210 and via hole 211. Ashing may or may not be then used to remove the resist layer 207.
One of the issues associated with various etching techniques, including but not limited to RIE, is the variance in selectivity during the etching process. For instance, the rate of etching may to some degree be related to a minimum cross sectional dimension. This means that layer 204 may etch faster over a via line (with a minimum dimension commonly around 100 nanometers) than over a via hole (with a minimum dimension commonly around 10 nanometers in diameter).
FIG. 2B shows a result of the differing etch rates. Here, while layer 204 was properly removed over line 202, at least a part of it (portion 213) remains over hole 203, thereby preventing complete contact with the metal contact 203.
A process is needed that accounts for the differing etch rates for via lines compared to via holes in semiconductor devices.